`timescale 1ns/1ps
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// -----------------------------------------------------------------------------
// Project Name : 
// Author 		: HiDark
// File   		: if2id.sv
// Create 		: 2023-04-20 12:12:34
// Revise 		: 2023-04-20 12:12:34
// Abstract 	: 
// -----------------------------------------------------------------------------
`include "defines.svh"

module if2id(
	input	logic					clk,    // Clock
	input	logic					rst_n,  // Synchronous reset active low
	input 	logic	[31:0]			PC,		//PC register
	input 	logic	[31:0]			instr,	// instr fetch
	input	logic 					refetch_flag,	
	input 	logic					PCjump_flag_pipe, // J/B
	
	output 	logic	[31:0]			PC_if2id,	
	output 	logic	[31:0]			instr_if2id		
	);

//=================================================================================
// Body
//=================================================================================

	// irom is drived by rdclk, so delayed by one cycle compared to PC
	always_ff @(posedge clk) begin 
		if(~rst_n) 
			PC_if2id   			<= `PC_BASEADDR;
		else if(!refetch_flag)
			PC_if2id   			<= PC;
	end

	assign	instr_if2id	=	PCjump_flag_pipe?`ZEROWORD:instr;


endmodule